Nexus S を 1.3GHz にクロックアップする

最近は、早起きして早朝に Nexus S のチューニングを進めているわけですが、今日は CPU Frequency Table に手を加えてしてクロックアップをしてみました。

まずは標準の 1.0GHz から 1.3GHz へのクロックアップを行います。こちらは、Galaxy S でも実績のある数値なので特に問題はないと思うのですが、下手したら確実に壊れます。この patch を元に壊して私は責任をとれませんのであしからず。

やってることは大したことはなくて、cpu_frequency_table に設定を追加しているだけです。ポイントは、その値に応じて供給電圧を変化させなければならない点です。逆にこの供給電圧を標準より下げることで、バッテリーの消費を減らすことができるようになります。コスタリカ産の Celeron 300A をクロックアップして動かしていた時代が思い出されます。

差分は以下の通りです。

arch/arm/mach-s5pv210/cpu-freq.c
--- a/arch/arm/mach-s5pv210/cpu-freq.c
+++ b/arch/arm/mach-s5pv210/cpu-freq.c
@@ -52,11 +52,12 @@ static DEFINE_MUTEX(set_freq_lock);
 
 /* frequency */
 static struct cpufreq_frequency_table freq_table[] = {
-       {L0, 1000*1000},
-       {L1, 800*1000},
-       {L2, 400*1000},
-       {L3, 200*1000},
-       {L4, 100*1000},
+       {L0, 1300*1000},
+       {L1, 1000*1000},
+       {L2, 800*1000},
+       {L3, 400*1000},
+       {L4, 200*1000},
+       {L5, 100*1000},
        {0, CPUFREQ_TABLE_END},
 };
 
@@ -70,46 +71,63 @@ const unsigned long int_volt_max = 1250000;
 
 static struct s5pv210_dvs_conf dvs_conf[] = {
        [L0] = {
-               .arm_volt   = 1250000,
-                .int_volt   = 1100000,
+               .arm_volt   = 1300000,
+                .int_volt   = 1200000,
        },
        [L1] = {
-               .arm_volt   = 1200000,
+               .arm_volt   = 1250000,
                .int_volt   = 1100000,
        },
        [L2] = {
-               .arm_volt   = 1050000,
+               .arm_volt   = 1200000,
                .int_volt   = 1100000,
        },
        [L3] = {
-               .arm_volt   = 950000,
+               .arm_volt   = 1050000,
                .int_volt   = 1100000,
        },
        [L4] = {
                .arm_volt   = 950000,
+               .int_volt   = 1100000,
+       },
+       [L5] = {
+               .arm_volt   = 950000,
                .int_volt   = 1000000,
        },
 };
 
-static u32 clkdiv_val[5][11] = {
+static u32 clkdiv_val[6][11] = {
        /*{ APLL, A2M, HCLK_MSYS, PCLK_MSYS,
         * HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS, ONEDRAM,
         * MFC, G3D }
         */
-       /* L0 : [1000/200/200/100][166/83][133/66][200/200] */
+       /* L0 : [1300/200/200/100][166/83][133/66][200/200] */
+       {0, 6, 6, 1, 3, 1, 4, 1, 3, 0, 0},
+       /* L1 : [1000/200/200/100][166/83][133/66][200/200] */
        {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
-       /* L1 : [800/200/200/100][166/83][133/66][200/200] */
+       /* L2 : [800/200/200/100][166/83][133/66][200/200] */
        {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
-       /* L2 : [400/200/200/100][166/83][133/66][200/200] */
+       /* L3 : [400/200/200/100][166/83][133/66][200/200] */
        {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
-       /* L3 : [200/200/200/100][166/83][133/66][200/200] */
+       /* L4 : [200/200/200/100][166/83][133/66][200/200] */
        {3, 3, 0, 1, 3, 1, 4, 1, 3, 0, 0},
-       /* L4 : [100/100/100/100][83/83][66/66][100/100] */
+       /* L5 : [100/100/100/100][83/83][66/66][100/100] */
        {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
 };
 
 static struct s3c_freq clk_info[] = {
-       [L0] = {        /* L0: 1GHz */
+       [L0] = {        /* L0: 1.3GHz */
+               .fclk       = 1300000,
+               .armclk     = 1000000,
+               .hclk_tns   = 0,
+               .hclk       = 133000,
+               .pclk       = 66000,
+               .hclk_msys  = 200000,
+               .pclk_msys  = 100000,
+               .hclk_dsys  = 166750,
+               .pclk_dsys  = 83375,
+       },
+       [L1] = {        /* L1: 1GHz */
                .fclk       = 1000000,
                .armclk     = 1000000,
                .hclk_tns   = 0,
@@ -120,7 +138,7 @@ static struct s3c_freq clk_info[] = {
                .hclk_dsys  = 166750,
                .pclk_dsys  = 83375,
        },
-       [L1] = {        /* L1: 800MHz */
+       [L2] = {        /* L2: 800MHz */
                .fclk       = 800000,
                .armclk     = 800000,
                .hclk_tns   = 0,
@@ -131,7 +149,7 @@ static struct s3c_freq clk_info[] = {
                .hclk_dsys  = 166750,
                .pclk_dsys  = 83375,
        },
-       [L2] = {        /* L2: 400MHz */
+       [L3] = {        /* L3: 400MHz */
                .fclk       = 800000,
                .armclk     = 400000,
                .hclk_tns   = 0,
@@ -142,7 +160,7 @@ static struct s3c_freq clk_info[] = {
                .hclk_dsys  = 166750,
                .pclk_dsys  = 83375,
        },
-       [L3] = {        /* L3: 200MHz */
+       [L4] = {        /* L4: 200MHz */
                .fclk       = 800000,
                .armclk     = 200000,
                .hclk_tns   = 0,
@@ -153,7 +171,7 @@ static struct s3c_freq clk_info[] = {
                .hclk_dsys  = 166750,
                .pclk_dsys  = 83375,
        },
-       [L4] = {        /* L4: 100MHz */
+       [L5] = {        /* L5: 100MHz */
                .fclk       = 800000,
                .armclk     = 100000,
                .hclk_tns   = 0,
@@ -269,6 +287,9 @@ static void s5pv210_cpufreq_clksrcs_MPLL2APLL(unsigned int index,
         * 2-1. Set PMS values
         */
        if (index == L0)
+               /* APLL FOUT becomes 1300 Mhz */
+               __raw_writel(PLL45XX_APLL_VAL_1300, S5P_APLL_CON);
+       else if (index == L1)
                /* APLL FOUT becomes 1000 Mhz */
                __raw_writel(PLL45XX_APLL_VAL_1000, S5P_APLL_CON);
        else
@@ -478,7 +499,7 @@ static int s5pv210_cpufreq_target(struct cpufreq_policy *policy,
                s5pv210_cpufreq_clksrcs_APLL2MPLL(index, bus_speed_changing);
 
        /* ARM MCS value changed */
-       if (index <= L2) {
+       if (index <= L3) {
                reg = __raw_readl(S5P_ARM_MCS_CON);
                reg &= ~0x3;
                reg |= 0x1;
@@ -508,7 +529,7 @@ static int s5pv210_cpufreq_target(struct cpufreq_policy *policy,
        } while (reg & 0xff);
 
        /* ARM MCS value changed */
-       if (index > L2) {
+       if (index > L3) {
                reg = __raw_readl(S5P_ARM_MCS_CON);
                reg &= ~0x3;
                reg |= 0x3;
@@ -543,7 +564,7 @@ static int s5pv210_cpufreq_target(struct cpufreq_policy *policy,
 
        /*
         * Adjust DMC1 refresh ratio according to the rate of hclk_msys
-        * (L0~L3: 200 <-> L4: 100)
+        * (L0~L4: 200 <-> L5: 100)
         * If DMC1 clock gets slower (by original clock speed * n),
         * then, the refresh rate should decrease
         * (by original refresh count * n) (n : clock rate)
@@ -603,9 +624,9 @@ static int s5pv210_cpufreq_resume(struct cpufreq_policy *policy)
 
        if (level == CPUFREQ_TABLE_END) { /* Not found */
                pr_err("[%s:%d] clock speed does not match: "
-                               "%d. Using L1 of 800MHz.\n",
+                               "%d. Using L2 of 800MHz.\n",
                                __FILE__, __LINE__, rate);
-               level = L1;
+               level = L2;
        }
 
        memcpy(&s3c_freqs.old, &clk_info[level],
@@ -656,9 +677,9 @@ static int __init s5pv210_cpufreq_driver_init(struct cpufreq_policy *policy)
 
        if (level == CPUFREQ_TABLE_END) { /* Not found */
                pr_err("[%s:%d] clock speed does not match: "
-                               "%d. Using L1 of 800MHz.\n",
+                               "%d. Using L2 of 800MHz.\n",
                                __FILE__, __LINE__, rate);
-               level = L1;
+               level = L2;
        }
 
        backup_dmc0_reg = __raw_readl(S5P_VA_DMC0 + 0x30) & 0xFFFF;
arch/arm/mach-s5pv210/include/mach/cpu-freq-v210.h
--- a/arch/arm/mach-s5pv210/include/mach/cpu-freq-v210.h
+++ b/arch/arm/mach-s5pv210/include/mach/cpu-freq-v210.h
@@ -29,6 +29,7 @@ enum perf_level {
        L2,
        L3,
        L4,
+       L5,
 };
 
 #define SLEEP_FREQ      (800 * 1000) /* Use 800MHz when entering sleep */
arch/arm/plat-s5p/include/plat/pll.h
--- a/arch/arm/plat-s5p/include/plat/pll.h
+++ b/arch/arm/plat-s5p/include/plat/pll.h
@@ -21,6 +21,7 @@
 
 #include 
 
+#define PLL45XX_APLL_VAL_1300  ((1 << 31) | (444 << 16) | (4 << 8) | (0))
 #define PLL45XX_APLL_VAL_1000  ((1 << 31) | (125 << 16) | (3 << 8) | (1))
 #define PLL45XX_APLL_VAL_800   ((1 << 31) | (100 << 16) | (3 << 8) | (1))
 

今日一日この設定で動かして様子を見て問題なさそうであれば、次回は電圧を下げてバッテリーの持ちを改善したいと思います。



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